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| Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. Using 'trench' technology the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in automotive and general purpose switching applications. BUK9675-55 QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 55 19.7 61 175 75 UNIT V A W C m PINNING - SOT404 PIN 1 2 3 mb gate drain source drain DESCRIPTION PIN CONFIGURATION mb SYMBOL d g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 10 19.7 13.9 79 61 175 UNIT V V V A A A W C ESD LIMITING VALUE SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint, FR4 board TYP. 50 MAX. 2.46 UNIT K/W K/W April 1998 1 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET STATIC CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Gate-source breakdown voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VDS = 55 V; VGS = 0 V; VGS = 5 V; VDS = 0 V IG = 1 mA; VGS = 5 V; ID = 10 A Tj = 175C Tj = 175C Tj = 175C MIN. 55 50 1 0.5 10 TYP. 1.5 0.05 0.02 60 - BUK9675-55 MAX. 2 2.3 10 500 1 10 75 157 UNIT V V V V A A A A V m m DYNAMIC CHARACTERISTICS Tmb = 25C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 10 A VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. 5 TYP. 500 110 60 10 47 28 33 2.5 7.5 MAX. 650 135 85 15 70 40 45 UNIT S pF pF pF ns ns ns ns nH nH VDD = 30 V; ID = 10 A; VGS = 5 V; RG = 10 Resistive load Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 19.7 A; VGS = 0 V IF = 19.7 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 30 V TYP. 0.95 32 0.12 MAX. 19.7 79 1.2 UNIT A A V ns C April 1998 2 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET AVALANCHE LIMITING VALUE SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 10 A; VDD 25 V; VGS = 5 V; RGS = 50 ; Tmb = 25 C MIN. TYP. - BUK9675-55 MAX. 30 UNIT mJ 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 100 tp = ID/A RDS(ON) = VDS/ID 10us 10 1 us 100 us DC 1 ms 10ms 100ms 1 10 0 20 40 60 80 100 Tmb / C 120 140 160 180 1 VDS/V 100 Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) Normalised Current Derating Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Zth/ (K/W) 120 110 100 90 80 70 60 50 40 30 20 10 0 ID% 10 1 0.5 0.2 0.1 0.05 P D tp D= tp T t 0.1 0.02 T 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.01 1.0E-06 0.0001 t/s 0.01 1 100 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T April 1998 3 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET BUK9675-55 50 ID/A 40 10.0 8.0 VGS/V = 6.0 5.4 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 10 2.0 15 14 13 12 11 10 9 8 7 6 5 Transconductance, gfs (S) 30 20 10 0 0 5 0 2 4 VDS/V 6 8 10 15 Drain current, ID (A) 20 25 Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS RDS(ON)/mOhm Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V BUK959-60 90 85 80 75 70 65 60 55 2.5 VGS/V = 4 4.2 4.4 4.6 4.8 5 a Rds(on) normlised to 25degC 2 1.5 1 5 10 15 ID/A 20 25 0.5 -100 -50 0 50 Tmb / degC 100 150 200 Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS 25 ID/A 20 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 10 A; VGS = 5 V VGS(TO) / V max. 2 typ. BUK959-60 2.5 15 1.5 min. 10 1 5 Tj/C = 0 0 1 175 2 25 VGS/V 3 4 5 0.5 0 -100 -50 0 50 Tj / C 100 150 200 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS April 1998 4 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET BUK9675-55 1E-01 Sub-Threshold Conduction 100 IF/A 80 1E-02 2% typ 98% 60 Tj/C = 40 175 25 1E-03 1E-04 1E-05 20 1E-05 0 0 0.5 1 1.5 2 2.5 3 0 0.5 VSDS/V 1 1.5 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS 1 .9 .8 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj WDSS% 120 110 100 90 80 70 Ciss Thousands pF .7 .6 .5 .4 .3 .2 .1 0 0.01 0.1 1 VDS/V 10 Coss Crss 100 60 50 40 30 20 10 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 6 VGS/V 5 VDS = 14V 4 VDS = 44V Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 17 A + L VDS VGS 0 RGS T.U.T. R 01 shunt VDD 3 -ID/100 2 1 0 0 2 4 6 QG/nC 8 10 12 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 20 A; parameter VDS Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) April 1998 5 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET BUK9675-55 + RD VDS VGS 0 RG T.U.T. VDD - Fig.17. Switching test circuit. April 1998 6 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g 10.3 max 4.5 max 1.4 max BUK9675-55 11 max 15.4 2.5 0.85 max (x2) 2.54 (x2) 0.5 Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". April 1998 7 Rev 1.100 Philips Semiconductors Product specification TrenchMOSTM transistor Logic level FET DEFINITIONS Data sheet status Objective specification Product specification Limiting values BUK9675-55 This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1998 8 Rev 1.100 |
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